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Full-time Design Verification System Verilog

at KBS Consultants (Anywhere)

Design Verification System Verilog

Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM).
Proficiency in one or more HVL's System Verilog, C++, Vera, e, System C, Test Builder is a must.
Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AMBA, PHY Layer is a must
Must be expert in building a verification environment with any of the above methodology, writing and debugging test cases.
Should be able to enhance the Verification Coverage, Code coverage & Functional Coverage.
Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc. is a must

SoC Verification Vera System Verilog
SoC Verification - Vera/ System Verilog
Experience : 5+years
Qualification : Any Engineering Graduate
Skill Set : SoC Verification, Vera, System Verilog

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Published at 27-03-2014
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