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Full-time Lead ASIC Physical design verification engineer

at KBS Consultants (Anywhere)

Lead ASIC Physical design verification engineer

Lead - Physical Design Verification Will be responsible for execution of Physical verification at Full chip and block level.
Will also be responsible for physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in Place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks.
Requirements: 5 years of ASIC physical verification and design experience.
Should have hands-on experience with Mentor/ Cadence tools for Physical verification and familiarity with Cadence physical design tools.
An exposure to DFM checks and analysis will be an added advantage.
This job will require interfacing with the design teams and our fab technology team to do sign off physical verification checks for multiple foundries.
A good understanding of layout DRC rules and concepts, device identification concepts. Should have participated in 3-4 full chip tapeouts.
Experience supporting layout teams and displaying solid programming knowledge in Perl, SKILL, TCL, and/or Shell Scripting, and the physical verification languages like SVRF, SKILL. Cadence DFII framework and understand basic concepts related to gate and device-level extraction.
Familiarity with various simulation / synthesis / formal verification tools.
Must have seen multiple ASIC tape-outs with at least 1 from RTL/Netlist to full production.

Email your resume to kbschennai@kbsconsultants.com


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Published at 27-03-2014
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